In recent years, a stacked semiconductor memory device has been proposed in which memory cells are integrated in a three-dimensional manner. In such a stacked semiconductor memory device, electrode films and insulating films are alternately stacked on a semiconductor substrate as a stacked body, and semiconductor pillars penetrate through this stacked body. Memory cell transistors are formed at intersections between the electrode films and the semiconductor pillars. In such a stacked semiconductor memory device, there is a problem in ensuring reliability.